1. Technical Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to estimating optimal gate sizes by using numerical delay models.
2. Related Art
The goal of circuit synthesis is to convert a high-level description of a circuit design into an implementation that meets a set of timing constraints, and at the same time optionally optimizes one or more metrics, such as area, leakage power, etc.
Some circuit synthesis approaches create an initial circuit design at a given abstraction level (e.g., a logical or physical design). Next, a cell is identified in the circuit design for optimization based on the metrics that are desired to be optimized. An optimal size for the identified cell is then determined by iteratively replacing the identified cell with functionally equivalent cells that have different sizes (this optimization process is also referred to as “sizing the cell,” “sizing the gate,” etc.). For each replacement cell size that is tried, the circuit synthesis approach updates timing information, and rejects cell sizes for which one or more timing constraints are violated. The iterative optimization process typically terminates after the optimization process has executed for a certain number of iterations or for a certain amount of time.
Unfortunately, such iterative trial-and-error based circuit synthesis approaches either take too long to complete and/or produce poor quality results for large circuit designs in which timing constraints are checked across many process corners and modes.
A circuit synthesis approach that is different from iterative trial-and-error approaches is described in Ivan Sutherland, Robert F. Sproull, and David Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann, 1999. This approach uses the following linear cell delay model:d=g·h+p,  (1)where, g represents the logical effort, h represents the electrical effort, and p represents the parasitic delay of the cell. The logical effort captures the effect of the cell's topology on its ability to produce output current. The logical effort is independent of the size of the transistors in the circuit. The electrical effort describes how the electrical environment of the cell affects performance, and how the size of the transistors in the cell determines its load-driving capability. The parasitic delay is a form of delay overhead that accompanies any gate.
Equation (1) can be rewritten as:d=R·Co+p,  (2)where, R is the output resistance of the cell, Co is the output loading, and p is the parasitic delay of the cell. Equation (2) can then be rewritten as:
                              d          =                                                    (                                  R                  ·                                      C                    i                                                  )                            ·                              (                                                      C                    o                                                        C                    i                                                  )                                      +            p                          ,                            (        3        )            where, Ci is the input capacitance presented by the cell at one of its input terminals. The first term (R·Ci) represents the logical effort g, and the second term
         (                  C        o                    C        i              )  represents the electrical effort h. The logical effort g and the parasitic delay p can be normalized, e.g., they can be normalized with respect to the logical effort and parasitic delay values, respectively, of a reference inverter.
The delay model that is used by a circuit synthesis approach must be accurate, i.e., it must accurately model the actual cell delays. If the delay model is inaccurate, the circuit implementation produced by the circuit synthesis approach will likely contain many timing violations.
In the above-mentioned work by Sutherland et al., the authors state that the linear delay model is approximate, and it does not accurately model the actual cell delays. Even if an accurate linear cell delay model is used in an iterative trial-and-error based circuit optimization process, the circuit optimization process could still take too long to complete and/or produce poor quality results for large circuit designs in which timing constraints are checked across many process corners and modes.